[PDF.70za] Formal Verification of a Processor with Memory Management Units: Hardware Design without Logical Bugs

Formal Verification of a Processor with Memory Management Units: Hardware Design without Logical Bugs

[PDF.yj28] Formal Verification of a Processor with Memory Management Units: Hardware Design without Logical Bugs

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 | #16520994 in Books |  2013-10-17 |  2013-10-17 | Original language:English | PDF # 1 |  8.66 x.28 x5.91l,.41 | File type: PDF | 120 pages

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||About the Author|I.Dalinger: Born in 1979. He received PhD degree from Saarland University in 2006. Now, he is deputy vice-president for science of Saint-Petersburg State University of Civil Aviation. A.Alekhin: Born in 1983. He received MSc degree in computer s

In this book we present the formal verification of a memory management unit which operates under specific conditions. We also present the formal verification of a complex processor VAMP with support of address translation by means of a memory management unit. The VAMP is an out-of-order 32-bit RISC CPU with a DLX instruction set, fully IEEE-compliant floating point units, and a memory unit. The VAMP also supports precise internal and external interrupts. It is modeled ...

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